TY  - BOOK
AU  - Uyemura J P
TI  - Chip Design for Submicron VLSI: CMOS Layout and Simulation
T2  - -
SN  - 9788131501955
PY  - 2009///
PB  - Cengage Learning
KW  - Electronics and Communication
KW  - VLSI
N1  - -
ER  -