| 000 | 00481nam a2200157Ia 4500 | ||
|---|---|---|---|
| 008 | 201210s9999||||xx |||||||||||||| ||und|| | ||
| 020 | _a978-3-319-02378-6 | ||
| 100 |
_aNoia _947271 |
||
| 245 | 0 | _aDesign-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs | |
| 250 | _a1 | ||
| 264 |
_bSpringer International Publishing _c2014 _dMonograph |
||
| 500 | _aFulltext | ||
| 546 | _aENG | ||
| 856 | _uhttp://link.springer.com/10.1007/978-3-319-02378-6 | ||
| 942 | _cEBK | ||
| 999 |
_c29065 _d29065 |
||